发明申请
- 专利标题： METHOD OF FORMING WIRINGS
- 专利标题（中）： 形成线的方法
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申请号： US14497501申请日： 2014-09-26
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公开(公告)号： US20150140810A1公开(公告)日： 2015-05-21
- 发明人: Sang-Hyun LEE , Myeong-Cheol KIM , Yoo-Jung LEE , IL-Sup KIM , Seung-Ju PARK
- 申请人： SAMSUNG ELECTRONICS CO., LTD.
- 优先权： KR10-2013-0145696 20131121
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L21/311
摘要：
A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.
公开/授权文献
- US09287161B2 Method of forming wirings 公开/授权日：2016-03-15
信息查询
IPC分类:
