发明申请
- 专利标题： VIA STRUCTURE, MEMORY ARRAY STRUCTURE, THREE-DIMENSIONAL RESISTANCE MEMORY AND METHOD OF FORMING THE SAME
- 专利标题（中）： 通过结构，记忆阵列结构，三维电阻记忆及其形成方法
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申请号： US14488300申请日： 2014-09-17
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公开(公告)号： US20150129827A1公开(公告)日： 2015-05-14
- 发明人: Frederick T. Chen , Tai-Yuan Wu , Yu-Sheng Chen , Wei-Su Chen , Pei-Yi Gu , Yu-De Lin
- 申请人： Industrial Technology Research Institute
- 主分类号： H01L27/24
- IPC分类号： H01L27/24 ; H01L45/00
摘要：
Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
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