Invention Application
- Patent Title: METHOD OF FORMING VIA HOLE
- Patent Title (中): 通过孔的形成方法
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Application No.: US14541148Application Date: 2014-11-14
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Publication No.: US20150072529A1Publication Date: 2015-03-12
- Inventor: Cheng-Han Wu , Chun-Chi Yu
- Applicant: UNITED MICROELECTRONICS CORP.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/311 ; H01L21/027

Abstract:
The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.
Public/Granted literature
- US09147601B2 Method of forming via hole Public/Granted day:2015-09-29
Information query
IPC分类: