- 专利标题: CONFIGURATION FOR POWER REDUCTION IN DRAM
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申请号: US14327127申请日: 2014-07-09
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公开(公告)号: US20140325136A1公开(公告)日: 2014-10-30
- 发明人: Andre Schaefer , John B. Halbert
- 申请人: Andre Schaefer , John B. Halbert
- 主分类号: G11C11/4074
- IPC分类号: G11C11/4074 ; G06F1/32
摘要:
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.
公开/授权文献
- US09361970B2 Configuration for power reduction in DRAM 公开/授权日:2016-06-07
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