发明申请
US20140091374A1 STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
有权
用于集成CMOS和Si纳米光子的应力工程多层
- 专利标题： STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
- 专利标题（中）： 用于集成CMOS和Si纳米光子的应力工程多层
-
申请号： US13629910申请日： 2012-09-28
-
公开(公告)号： US20140091374A1公开(公告)日： 2014-04-03
- 发明人: Solomon Assefa , Tymon Barwicz , Swetha Kamlapurkar , Marwan H. Khater , Steven M. Shank , Yurii A. Vlasov
- 申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L27/14
- IPC分类号： H01L27/14 ; H01L31/18
摘要：
A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.
公开/授权文献
信息查询
IPC分类:
