发明申请
- 专利标题: SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
- 专利标题(中): 半导体器件和形成绝缘层的半导体器件的应力消除形成方法
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申请号: US13333739申请日: 2011-12-21
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公开(公告)号: US20130113092A9公开(公告)日: 2013-05-09
- 发明人: Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
- 申请人: Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
- 申请人地址: SG Singapore
- 专利权人: STATS CHIPPAC, LTD.
- 当前专利权人: STATS CHIPPAC, LTD.
- 当前专利权人地址: SG Singapore
- 主分类号: H01L23/52
- IPC分类号: H01L23/52 ; H01L21/56 ; H01L21/78
摘要:
A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
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