Invention Application
- Patent Title: INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
- Patent Title (中): 具有垂直互连的集成电路包装系统及其制造方法
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Application No.: US13166802Application Date: 2011-06-22
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Publication No.: US20120326331A1Publication Date: 2012-12-27
- Inventor: Byung Joon Han , In Sang Yoon , JoHyun Bae
- Applicant: Byung Joon Han , In Sang Yoon , JoHyun Bae
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/50
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.
Public/Granted literature
- US08674516B2 Integrated circuit packaging system with vertical interconnects and method of manufacture thereof Public/Granted day:2014-03-18
Information query
IPC分类:
