发明申请
US20090270062A1 Passive Miser and Four-Phase Clocking Method and Apparatus 有权
无源智能和四相时钟方法与装置

  • 专利标题: Passive Miser and Four-Phase Clocking Method and Apparatus
  • 专利标题(中): 无源智能和四相时钟方法与装置
  • 申请号: US12108239
    申请日: 2008-04-23
  • 公开(公告)号: US20090270062A1
    公开(公告)日: 2009-10-29
  • 发明人: Fenghao MuFredrik Tillman
  • 申请人: Fenghao MuFredrik Tillman
  • 主分类号: H04B1/26
  • IPC分类号: H04B1/26 H03B21/00
Passive Miser and Four-Phase Clocking Method and Apparatus
摘要:
According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.
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