发明申请
US20090125794A1 ACS UNIT OF A VITERBI DECODER AND METHOD FOR CALCULATING A BIT ERROR RATE BEFORE A VITERBI DECODER
有权
VITERBI解码器的ACS单元和在VITERBI解码器之前计算位错误率的方法
- 专利标题: ACS UNIT OF A VITERBI DECODER AND METHOD FOR CALCULATING A BIT ERROR RATE BEFORE A VITERBI DECODER
- 专利标题(中): VITERBI解码器的ACS单元和在VITERBI解码器之前计算位错误率的方法
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申请号: US11938788申请日: 2007-11-13
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公开(公告)号: US20090125794A1公开(公告)日: 2009-05-14
- 发明人: Shu-Mei Li , Szu-Chung Chang
- 申请人: Shu-Mei Li , Szu-Chung Chang
- 申请人地址: TW Taipei City
- 专利权人: TENOR ELECTRONICS CORPORATION
- 当前专利权人: TENOR ELECTRONICS CORPORATION
- 当前专利权人地址: TW Taipei City
- 主分类号: H03M13/41
- IPC分类号: H03M13/41 ; G06F11/00
摘要:
An ACS unit of a Viterbi decoder and a method for calculating the bit error rate (BER) before Viterbi decoder are provided. The ACS unit includes a state calculator and a BER calculator. The state calculator calculates the state metric of a corresponding target state in the trellis diagram and selects one of two candidate source states as the selected source state of the target state. The state calculator also provides a selection signal indicating the selected source state. The BER calculator is coupled to the state calculator for providing the sum of the BER of the selected source state and the bit error count (BEC) of the transition from the selected source state to the target state as the BER of the target state.
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