发明申请
- 专利标题: CHARGE PUMP CIRCUIT WITH REDUCED PARASITIC CAPACITANCE
- 专利标题(中): 充电泵电路具有降低的PARASITIC电容
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申请号: US11926704申请日: 2007-10-29
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公开(公告)号: US20080111598A1公开(公告)日: 2008-05-15
- 发明人: Hiroshi YANAGIGAWA , Masayuki IDA , Kazunori DOI
- 申请人: Hiroshi YANAGIGAWA , Masayuki IDA , Kazunori DOI
- 申请人地址: JP Kanagawa
- 专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人地址: JP Kanagawa
- 优先权: JP2006-307358 20061114
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.
公开/授权文献
- US07439795B2 Charge pump circuit with reduced parasitic capacitance 公开/授权日:2008-10-21
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