Invention Application
- Patent Title: METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE
- Patent Title (中): 形成半导体器件双栅的方法
-
Application No.: US11614975Application Date: 2006-12-22
-
Publication No.: US20070148848A1Publication Date: 2007-06-28
- Inventor: Gyu Hyun Kim , Geun Min Choi , Baik II Choi , Dong Joo Kim , Ji Hye Han
- Applicant: Gyu Hyun Kim , Geun Min Choi , Baik II Choi , Dong Joo Kim , Ji Hye Han
- Applicant Address: KR Icheon-shi
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-shi
- Priority: KR2005-128307 20051222; KR2006-88631 20060913
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to first wet cleaning, second wet cleaning and dry cleaning.
Information query
IPC分类: