An exemplary crystal panel (100) includes a first substrate (110), a second substrate (120) having a common electrode (121), and a liquid crystal layer (130) interposed therebetween. The first substrate defines a plurality of pixel regions. Each of the pixel regions includes a thin film transistor (140), a protection layer (170), a passivation layer (150), a pixel electrode (160). The thin film transistor includes a source (142), a gate (141), and a drain (143). The protection layer is formed at the gate insulating layer at a position corresponding to the drain. The passivation layer is formed at the thin film transistor, and the passivation layer has a contact hole (148) at position corresponding to the drain. The pixel electrode is formed at the passivation layer and the pixel electrode contacts the drain via the contract hole.