A memory controller includes: a splitter which divides input pixel data, in which the number of bits of a first color component is I1 bits, the number of bits of a second color component is I2 bits, and the number of bits of a third color component is I3 bits, into a basic data portion and an extension data portion, the number of bits of the first color component being J1 bits, the number of bits of the second color component being J2 bits, and the number of bits of the third color component being J3 bits (J1+J2+J3=2M) in the basic data portion, and the number of bits of the first color component being K1 bits, the number of bits of the second color component being K2 bits, and the number of bits of the third color component being K3 bits (K1+K2+K3=2N) in the extension data portion; and an address generator which generates access addresses for writing the basic data portion into a basic data storage region of the memory and writing the extension data portion into an extension data storage region of the memory.