Invention Application
- Patent Title: Method for analyzing fail bit maps of wafers
- Patent Title (中): 分析晶圆故障位图的方法
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Application No.: US10865927Application Date: 2004-06-14
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Publication No.: US20050021303A1Publication Date: 2005-01-27
- Inventor: Hiroshi Matsushita , Kenichi Kadota
- Applicant: Hiroshi Matsushita , Kenichi Kadota
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Priority: JP2003-173838 20030618
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G06F11/30 ; G11C29/00 ; H01L21/02
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Abstract:
A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.
Public/Granted literature
- US07138283B2 Method for analyzing fail bit maps of wafers Public/Granted day:2006-11-21
Information query
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