Invention Application
US20050021303A1 Method for analyzing fail bit maps of wafers 失效
分析晶圆故障位图的方法

Method for analyzing fail bit maps of wafers
Abstract:
A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.
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