发明申请
US20040238964A1 Semiconductor device with interconnection structure for reducing stress migration
审中-公开
具有用于减少应力迁移的互连结构的半导体器件
- 专利标题: Semiconductor device with interconnection structure for reducing stress migration
- 专利标题(中): 具有用于减少应力迁移的互连结构的半导体器件
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申请号: US10855562申请日: 2004-05-28
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公开(公告)号: US20040238964A1公开(公告)日: 2004-12-02
- 发明人: Masaya Kawano , Yoshiaki Yamamoto , Takamasa Ito
- 申请人: NEC ELECTRONICS CORPORATION
- 申请人地址: null
- 专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人地址: null
- 优先权: JP2003-154728 20030530
- 主分类号: H01L021/4763
- IPC分类号: H01L021/4763
摘要:
The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.
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