- 专利标题: Variable error correction codeword packing to support bit error rate targets
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申请号: US17109376申请日: 2020-12-02
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公开(公告)号: US12106815B2公开(公告)日: 2024-10-01
- 发明人: Ravi Motwani , Pranav Kalavade , Rohit Shenoy , Rifat Ferdous
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Coproration
- 当前专利权人: Intel Coproration
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Jordan IP Law, LLC
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G06F12/0882 ; G11C29/14 ; G11C29/42 ; G11C29/44
摘要:
Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.
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