- 专利标题: Selective liner on backside via and method thereof
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申请号: US18358576申请日: 2023-07-25
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公开(公告)号: US12021119B2公开(公告)日: 2024-06-25
- 发明人: Lin-Yu Huang , Li-Zhen Yu , Chia-Hao Chang , Cheng-Chi Chuang , Kuan-Lun Cheng , Chih-Hao Wang
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Haynes and Boone, LLP
- 分案原申请号: US16944263 2020.07.31
- 主分类号: H01L29/08
- IPC分类号: H01L29/08 ; H01L23/528 ; H01L29/06 ; H01L29/78
摘要:
A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.
公开/授权文献
- US20230369401A1 SELECTIVE LINER ON BACKSIDE VIA AND METHOD THEREOF 公开/授权日:2023-11-16
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