- 专利标题： Redistribution layer (RDL) layouts for integrated circuits
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申请号： US18362730申请日： 2023-07-31
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公开(公告)号： US12021054B2公开(公告)日： 2024-06-25
- 发明人: Cheng-Yuan Li , Kuo-Cheng Lee , Yun-Wei Cheng , Yen-Liang Lin
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Slater Matsil, LLP
- 分案原申请号： US15965116 2018.04.27
- 主分类号： H01L23/00
- IPC分类号： H01L23/00
摘要：
Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
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