- 专利标题: Dispatch bandwidth of memory-centric requests by bypassing storage array address checking
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申请号: US17386115申请日: 2021-07-27
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公开(公告)号: US12019547B2公开(公告)日: 2024-06-25
- 发明人: Jagadish B. Kotra , John Kalamatianos , Gagandeep Panwar
- 申请人: Advanced Micro Devices, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Hickman Becker Bingham Ledesma LLP
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F9/30 ; G06F12/02 ; G06F12/06 ; G06F12/0815 ; G06F12/0817
摘要:
A technical solution to the technical problem of how to improve dispatch throughput for memory-centric commands bypasses address checking for certain memory-centric commands. Implementations include using an Address Check Bypass (ACB) bit to specify whether address checking should be performed for a memory-centric command. ACB bit values are specified in memory-centric instructions, automatically specified by a process, such as a compiler, or by host hardware, such as dispatch hardware, based upon whether a memory-centric command explicitly references memory. Implementations include bypassing, i.e., not performing, address checking for memory-centric commands that do not access memory and also for memory-centric commands that do access memory, but that have the same physical address as a prior memory-centric command that explicitly accessed memory to ensure that any data in caches was flushed to memory and/or invalidated.
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