A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.