- 专利标题: Structure and method for vertical tunneling field effect transistor with leveled source and drain
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申请号: US17406861申请日: 2021-08-19
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公开(公告)号: US11894448B2公开(公告)日: 2024-02-06
- 发明人: Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: HAYNES AND BOONE, LLP
- 分案原申请号: US13795240 2013.03.12
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L27/08 ; H01L21/8234 ; H01L27/092 ; H01L21/8238 ; H01L29/78 ; H01L49/02
摘要:
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
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