Invention Grant
- Patent Title: Chip scale package
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Application No.: US17993638Application Date: 2022-11-23
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Publication No.: US11887924B2Publication Date: 2024-01-30
- Inventor: Craig McAdam , Jonathan Taylor , Douglas Macfarlane , John Kerr , James Munger , John Pavelka , Steven A. Atherton
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic Inc.
- Current Assignee: Cirrus Logic Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00
Abstract:
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
Public/Granted literature
- US20230088252A1 CHIP SCALE PACKAGE Public/Granted day:2023-03-23
Information query
IPC分类:
