Invention Grant
- Patent Title: Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
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Application No.: US16240369Application Date: 2019-01-04
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Publication No.: US11830933B2Publication Date: 2023-11-28
- Inventor: Willy Rachmady , Gilbert Dewey , Jack T. Kavalieros , Aaron Lilak , Patrick Morrow , Anh Phan , Cheng-Ying Huang , Ehren Mannebach
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/66 ; H01L21/02 ; H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/786

Abstract:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.
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