- 专利标题： Computer system with redundancy having fail test mode
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申请号： US17243086申请日： 2021-04-28
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公开(公告)号： US11810634B2公开(公告)日： 2023-11-07
- 发明人: Sadayuki Okuma
- 申请人： MICRON TECHNOLOGY, INC.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Dorsey & Whitney LLP
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G11C29/38 ; G11C17/16 ; G11C29/14 ; G11C11/4096 ; G11C11/4093 ; G11C17/18
摘要：
Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.
公开/授权文献
- US20220351797A1 COMPUTER SYSTEM WITH REDUNDANCY HAVING FAIL TEST MODE 公开/授权日：2022-11-03
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