Invention Grant
- Patent Title: Package structure and testing method
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Application No.: US16812232Application Date: 2020-03-06
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Publication No.: US11733294B2Publication Date: 2023-08-22
- Inventor: Chen-Chao Wang , Tsung-Tang Tsai , Chih-Yi Huang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; G01R31/28 ; H01L23/538 ; H01L23/552 ; H01L25/18 ; H01L23/00 ; H01L21/56 ; H01L23/31

Abstract:
A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.
Public/Granted literature
- US20210278457A1 PACKAGE STRUCTURE AND TESTING METHOD Public/Granted day:2021-09-09
Information query
IPC分类: