Invention Grant
- Patent Title: Vertical junction to provide optimal transverse bias for dual free layer read heads
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Application No.: US17184541Application Date: 2021-02-24
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Publication No.: US11532324B2Publication Date: 2022-12-20
- Inventor: Ming Mao , Chen-Jung Chien , Daniele Mauri , Goncalo Marcos Baião De Albuquerque
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Agent Steven H. VerSteeg
- Main IPC: G11B5/39
- IPC: G11B5/39

Abstract:
The present disclosure generally relates to a read head assembly having a dual free layer (DFL) structure disposed between a first shield and a second shield at a media facing surface. The read head assembly further comprises a rear hard bias (RHB) structure disposed adjacent to the DFL structure recessed from the media facing surface, where an insulation layer separates the RHB structure from the DFL structure. The insulation layer is disposed perpendicularly between the first shield and the second shield. The DFL structure comprises a first free layer and a second free layer having equal stripe heights from the media facing surface to the insulation layer. The RHB structure comprises a seed layer, a bulk layer, and a capping layer. The capping layer and the insulation layer prevent the bulk layer from contacting the second shield.
Public/Granted literature
- US20220115035A1 Vertical Junction To Provide Optimal Transverse Bias For Dual Free Layer Read Heads Public/Granted day:2022-04-14
Information query
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