A controller for controlling a memory device comprising a plurality of multi-level cell memory blocks, the controller includes: a processor suitable for controlling the memory device to perform a read operation on a target logical page using some of the plurality of read voltages in a selected read voltage set; and an error correction code (ECC) component suitable for determining whether the read operation is successful, by performing error detection and correction on data generated in the read operation and output from the memory device, wherein, when the read operation is determined to be successful, the processor updates the selected read voltage set with the read voltages used in the read operation when it is successful and estimated values of unused read voltages of the selected read voltage set, the estimated values being determined based on the used read voltages.