- 专利标题: Phase lock loop (PLL) with operating parameter calibration circuit and method
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申请号: US17519122申请日: 2021-11-04
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公开(公告)号: US11418204B2公开(公告)日: 2022-08-16
- 发明人: Ankit Gupta
- 申请人: STMicroelectronics International N.V.
- 申请人地址: CH Geneva
- 专利权人: STMicroelectronics International N.V.
- 当前专利权人: STMicroelectronics International N.V.
- 当前专利权人地址: CH Geneva
- 代理机构: Crowe & Dunlevy
- 主分类号: H03L7/099
- IPC分类号: H03L7/099 ; H03L7/093 ; H03L7/089
摘要:
A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.
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