- 专利标题: Performing wear leveling operations in a memory based on block cycles and use of spare blocks
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申请号: US16523860申请日: 2019-07-26
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公开(公告)号: US11347402B2公开(公告)日: 2022-05-31
- 发明人: Domenico Monteleone , Giacomo Bernardi , Luca Porzio , Graziano Mirichigni , Stefano Zanardi , Erminio Di Martino
- 申请人: MICRON TECHNOLOGY, INC.
- 申请人地址: US ID Boise
- 专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人地址: US ID Boise
- 代理机构: Dorsey & Whitney LLP
- 主分类号: G06F3/06
- IPC分类号: G06F3/06 ; G06F12/02
摘要:
Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.
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