Methods, systems, and devices for capacitance allocation based on system impedance are described. A memory device may include a first voltage rail for distributing a first supply voltage to an array of memory cells. The memory device may be coupled with a circuit using a pad of the memory device; that is, the memory device may be coupled with other circuitry within a package or board. The memory device may determine an impedance associated with the circuit, and may couple one or more capacitors with the first voltage rail based on the impedance. The memory device may include a second voltage rail for distributing a second supply voltage to the array of memory cells. The memory device may compare the performance of the first and second voltage rails and couple one or more capacitors with the first voltage rail or the second voltage rail based on the comparison.