Invention Grant
- Patent Title: Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating
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Application No.: US16648640Application Date: 2017-12-30
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Publication No.: US11328996B2Publication Date: 2022-05-10
- Inventor: Veronica Strong , Aleksandar Aleksov , Brandon Rawlings
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/069155 WO 20171230
- International Announcement: WO2019/133017 WO 20190704
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/522 ; H01L23/00

Abstract:
A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.
Public/Granted literature
Information query
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