A failure analysis apparatus is an apparatus for analyzing a failure of a semiconductor device including a memory circuit and includes a storage device and a processor. The storage device stores EDA data including size values of a memory cell in the memory circuit, size values of a peripheral circuit in the memory circuit and arrangement spacing values of the peripheral circuit, and layout data of the semiconductor device. The processor converts logical addresses and I/O value of a fail bit obtained by testing the memory circuit into physical addresses using predetermined arithmetic expressions, and converts the physical addresses into physical coordinate values using the size values of the memory cell, the size values of the peripheral circuit, and the arrangement spacing values of the peripheral circuit.