Invention Grant
- Patent Title: Stacked capacitor
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Application No.: US16561593Application Date: 2019-09-05
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Publication No.: US11222841B2Publication Date: 2022-01-11
- Inventor: Poornika Fernandes , Ye Shao , Guruvayurappan S. Mathur , John K. Arch , Paul Stulik
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/522 ; H01G15/00 ; H01G4/06

Abstract:
An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
Public/Granted literature
- US20210074629A1 STACKED CAPACITOR Public/Granted day:2021-03-11
Information query
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