- 专利标题: Importing and exporting circuit layouts
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申请号: US16669320申请日: 2019-10-30
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公开(公告)号: US11204897B2公开(公告)日: 2021-12-21
- 发明人: Fu An Tien , Changsheng Ying , Hsu-Ting Huang , Ru-Gun Liu
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: McDermott Will & Emery LLP
- 主分类号: G06F16/174
- IPC分类号: G06F16/174 ; G06F16/16 ; G06F30/392 ; G06F30/34 ; G06F30/36 ; G06F30/39
摘要:
A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction. Multiple result files each in a compressed format are obtained from the distributed computing system and the result files are combined to obtain a single result file without decompressing and re-compressing the results from the distributed computing system.
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