A gate driver on array (GOA) driving circuit including a power management IC and a level shifter circuit connected in order, wherein the level shifter circuit at least includes a first switch transistor, a second switch transistor, a detection unit, and a clock signal output terminal, the first switch transistor is connected to the second switch transistor, and the clock signal output terminal is configured to connect to the GOA circuit, and wherein the detection unit is connected to the first switch transistor and the second switch transistor respectively, configured to detect power consumption of the first switch transistor and the second switch transistor and feedback a detection result that is configured to control an on/off state of a signal output of the power management IC.