Invention Grant
- Patent Title: Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
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Application No.: US16326679Application Date: 2016-09-29
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Publication No.: US11101222B2Publication Date: 2021-08-24
- Inventor: Srinivas V. Pietambaram , Sri Ranga Sai Boyapati , Robert A. May , Kristof Darmawikarta , Javier Soto Gonzalez , Kwangmo Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/054559 WO 20160929
- International Announcement: WO2018/063263 WO 20180405
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00

Abstract:
A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
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Information query
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