- 专利标题： System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
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申请号： US16040963申请日： 2018-07-20
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公开(公告)号： US10996634B2公开(公告)日： 2021-05-04
- 发明人: Chih-Wei Yao , Ronghua Ni
- 申请人： Samsung Electronics Co., Ltd.
- 申请人地址： KR Gyeonggi-do
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Gyeonggi-do
- 代理机构： The Farrell Law Firm, P.C.
- 主分类号： G04F10/00
- IPC分类号： G04F10/00 ; H03L7/091 ; H03M1/12 ; H03L7/089 ; H03L7/099 ; H03M1/48
摘要：
A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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