- Patent Title: Integration of magneto-resistive random access memory and capacitor
-
Application No.: US16045237Application Date: 2018-07-25
-
Publication No.: US10971544B2Publication Date: 2021-04-06
- Inventor: Chung-Cheng Chou , Ya-Chen Kao , Tien-Wei Chiang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/22
- IPC: H01L27/22 ; H01L43/12 ; H01L43/10

Abstract:
Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
Public/Granted literature
- US20180350877A1 Integration of Magneto-Resistive Random Access Memory and Capacitor Public/Granted day:2018-12-06
Information query
IPC分类: