Invention Grant
- Patent Title: Single pin test interface for pin limited systems
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Application No.: US15836363Application Date: 2017-12-08
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Publication No.: US10816597B2Publication Date: 2020-10-27
- Inventor: Huanhui Zhan , Krishna Pentakota , Stefan N. Mastovich
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/316

Abstract:
An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.
Public/Granted literature
- US20190178937A1 SINGLE PIN TEST INTERFACE FOR PIN LIMITED SYSTEMS Public/Granted day:2019-06-13
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