Invention Grant
- Patent Title: Standalone interface for stacked silicon interconnect (SSI) technology integration
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Application No.: US15237384Application Date: 2016-08-15
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Publication No.: US10784121B2Publication Date: 2020-09-22
- Inventor: Rafael C. Camarota
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/538 ; H01L21/48 ; H01L29/06 ; H01L25/18 ; H01L23/00

Abstract:
Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.
Public/Granted literature
- US20180047663A1 STANDALONE INTERFACE FOR STACKED SILICON INTERCONNECT (SSI) TECHNOLOGY INTEGRATION Public/Granted day:2018-02-15
Information query
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