A system includes memory dice, each having a register to store multiple read voltage levels. A processing device is to test each memory die by verification, via access to the multiple read voltage levels, whether each read voltage level falls within a corresponding relative voltage range. The processing device selects an initial read voltage level that achieves bit error rates not satisfying a threshold criterion at one of a first or a second shortest write-to-read (W2R) delay for the memory die and determines a bit error rate, using the initial read voltage level, of storage units of the memory die. The processing device reports the memory die as defective in response to one of: (i) a read voltage level, of the multiple read voltage levels, failing to verify; or (ii) the bit error rate of one or more storage units of the memory die satisfying the threshold criterion.