- 专利标题: Method of controlling wafer bow in a type III-V semiconductor device
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申请号: US15628723申请日: 2017-06-21
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公开(公告)号: US10720520B2公开(公告)日: 2020-07-21
- 发明人: Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
- 申请人: Infineon Technologies Austria AG
- 申请人地址: AT Villach
- 专利权人: Infineon Technologies Austria AG
- 当前专利权人: Infineon Technologies Austria AG
- 当前专利权人地址: AT Villach
- 代理机构: Murphy, Bilak & Homiller, PLLC
- 主分类号: H01L27/14
- IPC分类号: H01L27/14 ; H01L29/778 ; H01L21/02 ; H01L29/267 ; H01L29/20
摘要:
A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
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