- 专利标题： Apparatus for correcting a parallelism between a bonding head and a stage, and a chip bonder including the same
-
申请号： US15463061申请日： 2017-03-20
-
公开(公告)号： US10692833B2公开(公告)日： 2020-06-23
- 发明人: Jae-Cheol Kim , Gil-Man Kang , Kyoung-Bok Cho , Yong-Dae Ha
- 申请人： SAMSUNG ELECTRONICS CO., LTD.
- 申请人地址： KR Suwon-si, Gyeonggi-Do
- 专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址： KR Suwon-si, Gyeonggi-Do
- 代理机构： F. Chau & Associates, LLC
- 优先权： com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@23d77d8
- 主分类号： H01L21/00
- IPC分类号： H01L21/00 ; H01L23/00
摘要：
A bonding apparatus includes a detecting unit configured to determine whether a bonding head and a stage, on which a package substrate is disposed, are sufficiently parallel to each other during a bonding process, wherein the bonding head is configured to bond a semiconductor chip to the package substrate, and a correcting unit configured to adjust at least one of the bonding head or the stage based on the determination of the detecting unit during the bonding process.
公开/授权文献
信息查询
IPC分类:
