Invention Grant
- Patent Title: Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package
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Application No.: US15705543Application Date: 2017-09-15
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Publication No.: US10665534B2Publication Date: 2020-05-26
- Inventor: KyungHoon Lee , SangMi Park , KyoungIl Huh , DaeSik Choi
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: CN
- Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
- Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
- Current Assignee Address: CN
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L25/065 ; H01L21/56 ; H01L25/00 ; H01L23/00 ; H01L23/36 ; H01L23/31

Abstract:
A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.
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