Invention Grant
- Patent Title: Visible alignment markers/landmarks for CAD-to-silicon backside image alignment
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Application No.: US15265744Application Date: 2016-09-14
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Publication No.: US10605859B2Publication Date: 2020-03-31
- Inventor: Rami Salem , Lesly Zaren V. Endrinal , Hyeokjin Lim , Hadi Bunnalim , Robert Kim , Lavakumar Ranganathan , Mickael Malabry
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L23/50 ; H01L27/02 ; H01L27/088 ; G01R31/311 ; H01L23/544 ; H01L23/528 ; H01L27/118

Abstract:
A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.
Public/Granted literature
- US20180074117A1 VISIBLE ALIGNMENT MARKERS/LANDMARKS FOR CAD-TO-SILICON BACKSIDE IMAGE ALIGNMENT Public/Granted day:2018-03-15
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