- 专利标题： Self-aligned via below subtractively patterned interconnect
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申请号： US16070172申请日： 2016-03-30
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公开(公告)号： US10546772B2公开(公告)日： 2020-01-28
- 发明人: Manish Chandhok , Richard E. Schenker , Hui Jae Yoo , Kevin L. Lin , Jasmeet S. Chawla , Stephanie A. Bojarski , Satyarth Suri , Colin T. Carver , Sudipto Naskar
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt, P.C.
- 国际申请： PCT/US2016/025074 WO 20160330
- 国际公布： WO2017/171760 WO 20171005
- 主分类号： H01L23/52
- IPC分类号： H01L23/52 ; H01L21/768 ; H01L21/311 ; H01L23/522
摘要：
A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
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