Invention Grant
- Patent Title: Tag accelerator for low latency DRAM cache
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Application No.: US15855838Application Date: 2017-12-27
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Publication No.: US10545875B2Publication Date: 2020-01-28
- Inventor: Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Ganesh Balakrishnan , Ravindra N. Bhargava
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Meyertons Hood Kivlin Kowert & Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F12/0897
- IPC: G06F12/0897 ; G06F12/121

Abstract:
Systems, apparatuses, and methods for implementing a tag accelerator cache are disclosed. A system includes at least a data cache and a control unit coupled to the data cache via a memory controller. The control unit includes a tag accelerator cache (TAC) for caching tag blocks fetched from the data cache. The data cache is organized such that multiple tags are retrieved in a single access. This allows hiding the tag latency penalty for future accesses to neighboring tags and improves cache bandwidth. When a tag block is fetched from the data cache, the tag block is cached in the TAC. Memory requests received by the control unit first lookup the TAC before being forwarded to the data cache. Due to the presence of spatial locality in applications, the TAC can filter out a large percentage of tag accesses to the data cache, resulting in latency and bandwidth savings.
Public/Granted literature
- US20190196974A1 TAG ACCELERATOR FOR LOW LATENCY DRAM CACHE Public/Granted day:2019-06-27
Information query
IPC分类: