发明授权
- 专利标题： Method and system for automated selection of a subset of plurality of validation tests
-
申请号： US15978527申请日： 2018-05-14
-
公开(公告)号： US10528691B1公开(公告)日： 2020-01-07
- 发明人: Meir Ovadia
- 申请人： Cadence Design Systems, Inc.
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Pearl Cohen Zedek Latzer Baratz LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; G01R31/28
摘要：
A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one or a plurality of conditions.
信息查询
