Invention Grant
- Patent Title: Methods and articles for lapping stacked row bars having in-wafer ELG circuits
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Application No.: US15635414Application Date: 2017-06-28
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Publication No.: US10518381B2Publication Date: 2019-12-31
- Inventor: Gary J. Kunkel , Zoran Jandric
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Kagan Binder, PLLC
- Main IPC: B24B37/013
- IPC: B24B37/013 ; B24B37/04 ; G11B5/31 ; G11B5/60

Abstract:
A method of lapping multiple row bars provided in a stack, including the steps of electrically connecting at least one row bar bond pad of a first row bar to at least one carrier bond pad of a carrier, electrically connecting an outermost row bar of the stack to the first row bar of the stack by at least one electrical trace, wherein the outermost row bar comprises at least one electronic lapping guide, lapping an outer surface of the outermost row bar until a signal provided by the at least one electronic lapping guide of the outermost row bar reaches a predetermined value, terminating the lapping of the outermost row bar, and removing the outermost row bar from the stack to expose a second row bar, wherein the second row bar is electrically connected to the first row bar with the at least one electrical trace.
Public/Granted literature
- US20190001462A1 IN-WAFER ELG CIRCUITS AND METHODS FOR REDUCED BONDING Public/Granted day:2019-01-03
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