In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.